1. Field of the Invention
The present invention concerns a semiconductor device and a manufacturing method therefor and, particularly, it relates to a semiconductor device and a method of manufacturing the semiconductor device which is effective for bipolar transistors, MISFETs, (Insulated Gate Type Field Effect Transistors) and LSI (Large Scaled Semiconductor Integrated Circuit Devices). The present invention also relates to a semiconductor device having a TFT (Thin Film Transistor) or a high resistance element.
2. Description of the Prior Art
In the technology for semiconductor integrated circuit devices (IC), particularly, BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated circuits, it has been the general practice to form a P-type well, or trench, region on an N-type semiconductor substrate and to form an N-channel type MISFET in the P-well region.
A technique for forming a bipolar transistor instead of a CMOS inverter with low driving power, thereby constituting a power transistor in the final stage of an output section, etc., by utilizing the P-type well region is described in, for example, Japanese Patent Laid-Open Publication Sho 57-130461.
That is, in the CMOS integrated circuit, a P-type diffusion region as a base region is formed at the same time as the production step for the P-type well region on an N-type semiconductor substrate and an N.sup.+ region as an emitter region is formed at the same time as the formation of source and drain regions on the P-type diffusion region. It serves to provide an NPN-type bipolar transistor on the CMOS integrated circuit without altering the process at all.
Further, Japanese Patent Laid-Open Publication Sho 58-207671 discloses a semiconductor device having a base diffusion layer on one main surface of a semiconductor substrate and an emitter diffusion region formed in a portion of the surface thereof, in which a portion serving as an emitter diffusion mask formed on the base-emitter junction surface comprises a thin semiconductor oxide film and a polycrystalline semiconductor film formed thereon and the portion itself constitutes a peripheral portion of the emitter contact.
Furthermore, Japanese Patent Laid-Open Publication Sho 60-38856 discloses a method of manufacturing a semiconductor device in which an insulated gate electrode is formed with a polysilicon or metal silicide layer, a source and drain diffusion layer is formed by using the gate electrode and a field oxide film as a mask, and contacts and electrodes for each transistor are formed with a second polysilicon layer by way of an insulation film on the gate electrode, wherein a base diffusion layer as a base region is formed previously at an appropriate position of the substrate, a portion of the insulation film on the base diffusion layer is removed simultaneously with the formation of a contact hole for disposing source and drain electrodes made of polysilicon and, thereafter, a second polysilicon layer is deposited and an emitter diffusion layer is formed by thermal diffusion of impurity doped in the second polysilicon layer.
In each of the semiconductor devices described above, the N-type diffusion layer has been formed by implanting ions of a single impurity element belonging to group V of the Periodical Table, for example As (arsenic), P (phosphorus), or Sb (antimony). Further, an element belonging to the group V, for example P or As, has been introduced into the N-type diffusion layer in silicon. However, if the group V element is present at a high concentration, secondary defects are present in the high concentration region after heat treatment. For example, in the case of implanting As at 4.times.10.sup.15 cm.sup.-2 in a silicon substrate, followed by annealing, secondary defects are present in the region at the boundary between single crystals and amorphous material (a-C) and a region in which As is present at a concentration higher than 5.times.10.sup.20 cm.sup.-3 upon implantation. Further, for the As redistribution, As at high concentration causes accelerated diffusion to result in increased As redistribution. Accordingly, the secondary defects impair the reliability of the semiconductor device and the As redistribution hinders miniaturization and increase in the integration degree of the semiconductor device. The secondary defects and the redistribution are also present for other group V elements, that is, P and Sb.
Further, for a MISFET in an IC using, for example, a silicon substrate, a gate insulation film comprising a silicon oxide film is formed by thermally oxidizing the silicon substrate, and a gate electrode composed, for example, of polycrystalline silicon is formed on the gate insulation film. However, the boundary between the substrate and the gate insulation film, between the substrate and the element isolating insulation film, or between the gate insulation film and the gate electrode is not stable, which renders the electric characteristics of the MISFET instable during operation of the IC. For instance, there has been a problem of degradation in the threshold value voltage or current gain coefficient. Although the boundary can be stabilized by H.sub.2 forming gas sintering, Si--H bond is weak so that degradation in the characteristics of MISFETs has not yet been reduced completely.
Furthermore, TFTs used for liquid crystal television sets or TFTs and high resistance elements used for LSIs such as SRAMs use a thin film of polycrystalline silicon or amorphous silicon merely introduced with an impurity of a group III or V element.
Further, silicide layers of metal, for example Ti (titanium), Mo (molybdenum), W (tungsten), Ta (tantalum), Pt (platinum), Pd (palladium), Zr (zirconium), etc., are used as a portion of the gate electrode or the source and drain region. However, the diffusion of a group V impurity (P or As) in the silicide layer is extremely fast and it is impossible to dope the group V impurity selectively, for example, only in the N-type region by heat treatment through the silicide during manufacture of LSI. For instance, in a gate electrode comprising a dual lamination layer of polycrystalline silicon and metal silicide (polycide), group V element ions (As) selectively implanted into an N-type MISFET region are diffused into the metal silicide by the subsequent heat treatment, and reach as far as a P-type MISFET region, causing As doping also into the polycrystalline silicon of the gate electrode in the P-type region, thereby deteriorating the electric characteristics of the P-type MISFET.
In this way, secondary defects are created in a high concentration region in the diffusion layer comprising a group V impurity at a high concentration.
Further, the group V impurity at high concentration cause accelerated diffusion upon annealing, making it difficult for the formation of a shallow junction. Further, since the group V element causes violent redistribution in polycrystalline Si, refractory metal and refractory metal silicide, miniaturization for contacts or elements is impossible.
Further, upon forming an N-type diffusion layer by ion implantation, since secondary defects are also present at the boundary between amorphous and single crystals upon an implantation, there has been a problem that the performance of the element is deteriorated.